The invention grew out of needs associated with thin film transistors (TFTs) and their usage and fabrication in high-density static random access memories (SRAMs).
FIG. 1 is a schematic of a typical SRAM cell in accordance with the prior art and aspects of the invention, and is generally designated by reference numeral 10. Static memory cell 10 generally comprises first and second inverters 12 and 14 which are cross-coupled to form a bistable flip-flop. Inverters 12 and 14 are formed by a pair of channel driver or pull-down transistors 16 and 17, and p-channel load transistors 18 and 19. Driver transistors 16 and 17 are typically metal oxide silicon field effect transistors (MOSFETs) formed in a single crystal silicon semiconductor substrate. This type of transistor is sometimes referred to as a "bulk" device because its active regions are formed in the bulk substrate. P-channel transistors 18 and 19 are typically thin film transistors formed in a thin layer of polysilicon above the driver transistors.
The source regions of driver transistors 16 and 17 are tied to a low reference or circuit supply voltage, labelled V.sub.SS and typically referred to as "ground." Load transistors 18 and 19 preferably share a common thin film source and are connected in series between a high reference or circuit supply voltage, labelled V.sub.CC, and the drains of the corresponding driver transistors 16 and 17. The gates of load transistors 18 and 19 are connected to the gates of the corresponding driver transistors 16 and 17. The physical construction of many semiconductor memory cells allow a common transistor gate conductor to be used to gate corresponding driver and load transistors, as well known to people of skill in the art.
Inverter 12 has an inverter output 20 formed by the drains of driver transistor 16 and load transistor 18. Similarly, inverter 14 has an inverter output 22 formed by the drains of driver transistor 17 and load transistor 19. Inverter 12 has an inverter input 24 formed by the gate of driver transistor 16 and load transistor 18. Inverter 14 has an inverter input 26 formed by the gate of driver transistor 17 and load is transistor 19.
The inputs and outputs of inverters 12 and 14 are cross-coupled to form a flip-flop having a pair of complementary two-state outputs. Specifically, inverter output 20 is cross-coupled to inverter input 26, and inverter output 22 is cross-coupled to inverter input 24. In this configuration, inverter outputs 20 and 22 form the complementary two-state outputs of the flip-flop.
A memory flip-flop such as that described typically forms one memory element of an integrated array of static memory elements. A plurality of access transistors, such as access transistors 30 and 32, are used to selectively address and access individual memory elements within the array. Access transistor 30 is an n-channel MOSFET having one active terminal connected to cross-coupled inverter output 20. Access transistor 32 is an n-channel MOSFET having one active terminal connected to cross-coupled inverter output 22. A plurality of complementary or "split" column line pairs, such as the single pair of column lines 34 and 36 shown, are connected to the remaining active terminals of access transistors 30 and 32, respectively. A row line 38 is connected to the gates of access transistors 30 and 32.
Reading static memory cell 10 requires activating row line 38 to connect inverter outputs 20 and 22 to column lines 34 and 36. Writing to static memory cell 10 requires first placing selected complementary logic voltages on column lines 34 and 36, and then activating row line 38 to turn on the access transistors 30 and 32 to connect those logic voltages to inverter outputs 20 and 22. This forces the outputs to the selected logic voltages, which will be maintained as long as power is supplied to the memory cell, or until the memory cell is reprogrammed.
Preferably in accordance with the prior art and invention, transistor fabrication occurs by split gate processes. Such are defined as processes where the n-channel gate poly and p-channel gate poly are patterned using masks and etch steps at different points in the process sequence. This has a number of advantages. First, it allows individual tailoring of the n-channel device and p-channel device gate dimensions. Second, it reduces overall mask count by eliminating separate n-channel and p-channel lightly doped drain, n+ and p+ masks. Third, it allows p-channel formation to occur much later in the process sequence, which provides shallower p+ junctions and therefore higher performance p-channel devices.
A common material for thin film load transistors 18 and 19 is p-doped polysilicon. The thin film layer is typically 500 Angstroms or less in thickness. The n-layer is preferably fabricated such that a common source is formed for illustrated load transistors 18 and 19. The V.sub.CC potential is sent into the array onto a portion of the thin film polysilicon layer which is utilized in part as the common source in order to simplify the process. In this manner, an additional layer is not required to bring V.sub.CC to the cell.
A major problem in this approach is making ohmic contact to the p+ doped common source V.sub.CC formed on the thin film transistor layer. Such is typically accomplished by metallization contacts which are formed to make connection to the p+ common source thin film, to n+ active areas formed elsewhere in the base silicon substrate, and to gate poly layers. Due to the n+ active areas provided in the substrate, a contact etch of sufficient duration must be utilized to reach the silicon surface. However, the thin V.sub.CC P+ polysilicon layer typically lies well above the base silicon substrate. Accordingly, the thin polysilicon layer will experience significant over-etch exposure while deeper contacts are being simultaneously formed to the lower n + active areas.
The subject problem will be better understood by reference to FIG. 2. There illustrated are two fragmented sections of a semiconductor wafer 40, having a common bulk substrate region 42, field oxide regions 43 and other intervening layers indicated generally by reference numeral 44. A thin film transistor layer 45 is provided atop layers 44 and is intended to be representative of a common source area for the FIG. 1 transistors 18 and 19, or a thin film extension therefrom. An n+ diffusion region 46 is provided within base substrate 42. The intent is to provide V.sub.CC node interconnection to each of region 46 and thin film layer 45 by an interconnecting line.
An insulating dielectric layer 47 is provided over region 46 and thin film layer 45 as shown. A photoresist etch masking layer 50 is provided. A pair of contacts 48 and 49 are etched through layer 47 inwardly in the direction of diffusion region 46 and a target area for thin film layer 45, respectively. Once the illustrated etch reaches the outer surface of layer 45, as shown, the polysilicon of layer 45 is subjected to etching conditions. The etching conditions are preferably selected such that the etch rate of layer 47 (typically oxide) is significantly larger than the etch rate of polysilicon layer 45. However, in spite of the relative high selectivity, the very thin nature of layer 45 typically results in etching occurring completely through thin film layer 45, as shown in FIG. 3.
In a worse case scenario, contact opening 49 would undesirably be etched all the way into bulk substrate 42 (not shown). This would result in an undesired and fatal V.sub.CC -to-substrate short. In a best case scenario under the circumstances, the etch to produce contacts 48 and 49 will stop such that contact opening 49 terminates above bulk substrate region 42, as shown. However, this is still undesired as the metallization layer later deposited makes poor surface area contact to thin film layer 45 due to minimum sidewall contact with layer 45 as opposed to outer surface contact. Such can reduce the contact area to layer 45 by a factor of 2.5 or more. Further, titanium which is usually sputtered into the contact to improve contact conductance and provide a glue layer (not shown) for a subsequent tungsten plug, has poor step coverage. This may result in little or no sidewall titanium in the region of thin film layer 45, thereby increasing the chance than no ohmic contact is formed.
A prior art solution to the problem illustrated by FIGS. 2 and 3 is described with reference to FIG. 4. Such illustrates a wafer fragment 52 comprised of a bulk substrate 53 and associated field oxide regions 54. Like numbers from FIGS. 2 and 3 are utilized with the suffix "a" where appropriate. The intent of this method is essentially to provide a manner by which the thin film transistor layer 45a is brought inwardly in the direction of silicon substrate 53 such that the etch to produce contacts 48a and 49a is conducted to essentially the same depth. Field oxide 54 is formed to provide a gap or opening inwardly to what would typically be an n-well within bulk substrate 53. Immediately thereafter and prior to removal of the mask, p-type doping is conducted to produce the illustrated p+diffusion region 55. The n-well of substrate 53 would constitute n-type silicon, thereby providing diode electrical isolation between diffusion region 55 and the n-well.
Next, an oxide layer 56 is provided. A contact opening 57 is provided therethrough to diffusion region 55. P-type thin film poly layer 45a is then deposited and patterned, followed by deposition of insulating layer 47a. Subsequent patterning and etching are conducted to produce contact openings 48a and 49a. Contact opening 49a extends downwardly through layer 47a and layer 56 to outwardly expose diffusion region 55. A subsequently deposited and patterned metal layer 58 provides desired electrical interconnection of diffusion regions 55 and 46a to V.sub.CC. Accordingly, ohmic electrical interconnection occurs between polysilicon thin film layer 45a and conductive material within contact opening 49a through p+ diffusion region 55.
One disadvantage to this process is the large surface area, and correspondingly wafer real estate consumed, required to provide a connection to thin film layer 45a through diffusion region 55. Another disadvantage is that in the preferred split gate process, p-channel bulk devices must be formed before the thin film transistors in order to provide the p+ active area 55 without additional masking steps. This undesirably subjects the p-channel devices to more thermal processing than is desired.
It would be desirable to overcome these and other problems associated with the prior art processes and constructions. While the invention was motivated by processes associated with SRAM formation, the artisan will appreciate that aspects of the invention have applicability to other methods and constructions. The invention is intended to be limited only by the accompanying claims appropriately interpreted in accordance with the Doctrine of Equivalents.